1. Field of the Invention
The present invention relates generally to semiconductor device fabrication, and more specifically to auto defect screening in the manufacturing flow of fabricating semiconductor devices.
2. Description of Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Semiconductor devices are manufactured by fabricating many layers of circuit patterns on wafers to form a massive number of transistors for integration as complicated circuits. In the manufacturing flow of semiconductor devices, lithographic process (LP) is responsible for transferring circuit patterns created by circuit designers onto wafers.
Photomasks/reticles with opaque and clear patterns according to the circuit patterns are used for patterning device layers on wafers. Distortion of the patterns can result from the effect of the neighboring patterns on the photomask and optical diffraction, photoresist development and etching, chemical-mechanical polishing (CMP) on adjacent layers of the wafer, and geometric and overlaying relationships between patterns of adjacent layers fabricated on the wafer. As the component density of the integrated circuits (ICs) has increased the complexity of the IC patterns and layouts, systematic defects resulting from distortion of patterns or random defects resulting from process variation or contamination can fail the device fabricated on the wafer.
Wafer inspections on various patterned layers are routinely adopted in the production flow of manufacturing semiconductor devices. Optical inspection that has throughput of more than one full wafer per hour is the major work force in wafer inspection. In a typical wafer inspection, defects are detected along with nuisances which may be false alarms or defects of no interests. As the design rule shrinks, the sizes of many critical defects are also smaller and the signals of defects become weaker in comparison to signals of noise and normal process variation. As a result, a huge number of nuisances are often reported before a small number of critical defects of interest can be detected in the advanced technology nodes. It is a challenge for semiconductor device manufacturers to identify those critical defects of interest during both ramp-up and mass production periods of the manufacturing process.
In an optical inspection tool, nuisance filtering technique has been provided in a more advanced inspection recipe to help reduce the number of nuisances. In order to take advantage of the nuisance filtering technique, users have to carefully analyze and review the inspection results collected from one or more wafers using various defect analysis tools or a scanning electron microscope (SEM) review station to label each defect candidate as being a real defect or nuisance. The labelled real defects and nuisances are used to generate a nuisance filter. The nuisance filter is then included in the advanced recipe of the inspection tool to filter out the nuisances.
As the device technology advances to 20 nm and below, in order to retain critical defects of interest, the number of nuisances detected in the wafer inspection usually represents more than 90% of the reported defects from an optical inspection tool even after the nuisance filtering technique has been applied. The performance of the nuisance filtering technique cannot achieve the desired result of effectively filtering out the nuisances for several reasons.
One is that it is practically impossible to collect adequate critical defect types for generating the nuisance filter from a small number of inspected wafers. Another reason is that optical patches collected for inspection cannot resolve circuit patterns and can only provide very limited information at the advanced technology nodes. In addition, the massive amount of data that an inspection tool has to process in order to meet the required high throughput also limit the complexity of the affordable computation of the nuisance filter in the inspection. Furthermore, the continuing variation in the process window may also change the behavior of the nuisances and trigger new defect types that make the nuisance filer obsolete and not effective. As a result, the inspection tool still has to output a large number of nuisances in order to not miss critical defects of interest.
Therefore, during the ramp-up period, a large number of engineers and operators are dedicated to visually review the inspection result using SEM review tool in order to screen out the critical defects of interest to diagnose and improve the yield of the manufacturing process. During the mass production period, a small number of defects are usually sampled for SEM review to control the manufacturing process assuming that most of critical defects have been eliminated in the ramp-up period. As a result, there is significant risk for the semiconductor device manufactures to discover unknown critical defects only after the yield of the manufactured semiconductor device has been significantly impacted.